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HD74LS122
Retriggerable Monostable Multivibrator (with Clear)
REJ03D0428-0200 Rev.2.00 Feb.18.2005 This d-c triggered multivibrator features output pulse width control by three method. The basic pulse time is programmed by selection of external resistance and capacitance values. The HD74LS122 has internal timing resistor that allows the circuit to be used with only an external capacitor, if so desired. Once triggered, the basic pulse width may be extended by retriggering the gated low-level -active (A) or high-level active (B) inputs or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear. This device is provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 mV/ns.
A = "L" Clear = "H" Retrigger Pulse "H" B "L" tw + tPLH "H" Q tw Output without retrigger A = "L" "H" B "L" "H" Clear "L" "H" Q "L" Output without clear "L"
Figure 1
Typical Input / Output Pulse
Rev.2.00, Feb.18.2005, page 1 of 7
HD74LS122
Features
* Ordering Information
Part Name HD74LS122P HD74LS122FPEL Package Type DILP-14 pin SOP-14 pin (JEITA) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) Package Abbreviation P Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
PRSP0014DF-B FP (FP-14DAV) Note: Please consult the sales office for the above package availability.
Pin Arrangement
A1 A2 B1 B2 CLR Q GND
1 2 3 4 5 6 7 CLR Q Q
14 13 12 11 10 9 8
VCC Rext/Cext NC Cext NC Rint Q
(Top view)
Function Table
Inputs Clear A1 A2 L X X X H H X X X X X X H L X H L X H X L H X L H H H H H L X X L Notes: H; high level, L; low level, X; irrelevant ; transition from low to high level ; transition from high to low level ; one high-level pulse ; one low-level pulse Outputs B1 X X L X H H H H H H H B2 X X X L H H H H H H H Q L L L L Q H H H H
Rev.2.00, Feb.18.2005, page 2 of 7
HD74LS122
Block Diagram
External parameter Cext Rect /Cext Rint
A1 A2 B1 B2
Q
Q
Q CLR Clear
Q
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Input pulse width External timing resistance External capacitance Wiring capacitance at Rext/Cext terminal Symbol VCC IOH IOL Topr tw Rext Cext Rext/Cext -- Min 4.75 -- -- -20 40 5 Typ 5.00 -- -- 25 -- -- Non restriction -- 50 pF Max 5.25 -400 8 75 -- 260 Unit V A mA C ns k
Rev.2.00, Feb.18.2005, page 3 of 7
HD74LS122
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II min. 2.0 -- 2.7 -- -- -- -- -- typ.* -- -- -- -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 Unit V V V V A mA mA Condition
Input current
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V
Short-circuit output -20 -- -100 mA VCC = 5.25 V IOS current Supply current** ICC -- 6 11 mA VCC = 5.25 V Input clamp voltage VIK -- -- -1.5 V VCC = 4.75 V, IIN = -18 mA * VCC = 5 V, Ta = 25C ** With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. Note: To measure VOH at Q, VOL at Q, or IOS at Q, ground Rext / Cext, apply 2 V to B and clear, and pulse A from 2 V to 0 V.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Symbol tPLH tPHL tPLH tPHL tPLH tPHL t(out)min t(out) Inputs A B Clear Outputs Q Q Q Q Q Q Q Q min. -- -- -- -- -- -- -- 4 typ. 23 32 23 34 20 28 116 4.5 max. 33 45 44 56 27 45 200 5 Unit Condition
Propagation delay time
ns
Cext = 0, Rext = 5 k, CL = 15 pF, RL = 2 k
Output pulse width
A or B
s
Cext = 1000 pF, Rext = 10 k, CL = 15 pF, RL = 2 k
Rev.2.00, Feb.18.2005, page 4 of 7
HD74LS122
Typical Application Data for HD74LS122
For pulse widths when Cext 1000 pF, See Figure 3. The output pulse is primarily a function of the external capacitor and resistor. For Cext > 1000 pF, the output pulse width (tw) is defined as: tw(out) = K * Rext * Cext; See Figure 4.
VCC
Rext
+ -
Cext Rext (k) Cext (pF) tw(out) (ns)
to Cext
to Rext/Cext
Figure 2
Timing Component Connections
100,000
Output pulse width tw (ns)
Rext = 160k
10,000
1,000
Rext = 80k 40k 20k 10k 5k
100
10 1 10
100
1,000
External capacitance Cext (pF)
Figure 3
Typical Output Pulse Width (Cext 1000 pF)
0.5
A coefficient of output pulse width K
0.4 0.3 0.2 0.1 0
VCC = 5V Ta = 25C
103 2 3
5 7104 2 3
5 7105 2 3
5 7106 2 3
5 7107
Timing capacitance Cext (pF)
Figure 4
Rev.2.00, Feb.18.2005, page 5 of 7
Cext vs. K (Cext > 1000 pF)
HD74LS122
Testing Method
Test Circuit
VCC Output Q A1 Input P.G. Zout = 50 B1 Input P.G. Zout = 50 CLR Input P.G. Zout = 50 Q CLR Output Q Same as Load Circuit 1. 4.5V Cext Rext /Cext VCC RL Q CL Cext Rext Load circuit 1
H2
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Waveform
tw (in) A 40ns 1.3V 1.3V tw (in) 40ns B 1.3V 1.3V 0V tw (in) 40ns 1.3V tw (in) 40ns tw (CLR) 40ns Clear 1.3V 1.3V 0V tPLH Q 1.3V tPHL tPLH Q 1.3V tPHL 1.3V tPHL 1.3V tPLH VOH 1.3V tw (out) tw (out) 1.3V 1.3V VOL VOH 1.3V VOL 3V 1.3V 0V 3V 3V
Note:
Input pulse; tTLH 15 ns, tTHL 6 ns.
Rev.2.00, Feb.18.2005, page 6 of 7
HD74LS122
Package Dimensions
JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g
D
14
8
1 b3
7
Z
E
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 2.39 2.54 0.56 Max
A
A1
e1 D E
L
A A1 bp
e
bp
e1
c
b3 c
e Z
( Ni/Pd/Au plating )
L
JEITA Package Code P-SOP14-5.5x10.06-1.27
RENESAS Code PRSP0014DF-B
Previous Code FP-14DAV
MASS[Typ.] 0.23g
*1
D 8
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
14
bp
HE
E
Index mark
*2
c
Reference Symbol
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
7 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 1.42 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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